The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Mar. 30, 2022
Applicant:

Denso Corporation, Kariya, JP;

Inventors:

Daisuke Fukuoka, Kariya, JP;

Tomomi Okumura, Kariya, JP;

Yuuji Ootani, Kariya, JP;

Wataru Kobayashi, Kariya, JP;

Takumi Nomura, Kariya, JP;

Tomoaki Mitsunaga, Kariya, JP;

Takahiro Hirano, Kariya, JP;

Takamichi Sakai, Kariya, JP;

Kengo Oka, Kariya, JP;

Assignee:

DENSO CORPORATION, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H02P 27/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/4825 (2013.01); H01L 23/3107 (2013.01); H01L 23/49513 (2013.01); H01L 23/4952 (2013.01); H01L 23/49562 (2013.01); H01L 23/49568 (2013.01); H01L 23/49575 (2013.01); H02P 27/06 (2013.01);
Abstract

In a semiconductor device, a semiconductor element has a front electrode and a back electrode. The back electrode is connected to a wiring member through a bonding member. Wire pieces are disposed in the bonding member, and bonded to a bonding surface of the wiring member to protrude toward the semiconductor element. The bonding member has, in a plan view, a central region that overlaps with a central portion of the semiconductor element including an element center, and an outer peripheral region that includes a portion overlapping with an outer peripheral portion of the semiconductor element surrounding the central portion and surrounds the central region. At least four wire pieces are disposed in the outer peripheral region at positions corresponding to at least four respective corners of the semiconductor element. At least one wire piece is disposed to extend toward the element center in the plan view.


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