The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

May. 30, 2024
Applicant:

Georgia Tech Research Corporation, Atlanta, GA (US);

Inventors:

Nobuo Ogura, Tokyo, JP;

Siddharth Ravichandran, Atlanta, GA (US);

Venkatesh V. Sundaram, Atlanta, GA (US);

Rao R. Tummala, Atlanta, GA (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/4803 (2013.01); H01L 21/4857 (2013.01); H01L 21/56 (2013.01); H01L 23/3107 (2013.01); H01L 23/49827 (2013.01); H01L 23/562 (2013.01);
Abstract

Semiconductor packages and, more particularly, chip-embedded semiconductor packages. The packages include core panels with apertures extending through the core panel. Semiconductor chips are embedded within chip apertures. A molding compound can be positioned along one side of the core panel. The semiconductor chips can be embedded within the molding compound. The semiconductor chips also can be adhered to the molding compound. The coefficient of thermal expansion (CTE) values of the core panels can be tailored to decrease warpage of the package as the semiconductor chip heats during use.


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