The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Mar. 28, 2023
Applicant:

Intel Ndtm Us Llc, Santa Clara, CA (US);

Inventors:

Mattia Cichocki, Rome, IT;

Violante Moschiano, Avezzano, IT;

Tommaso Vali, Sezze, IT;

Guido Luciano Rizzo, Albignasego, IT;

Chang Wan Ha, San Ramon, CA (US);

Richard Fastow, Cupertino, CA (US);

Assignee:

Intel NDTM US LLC, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/24 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01);
Abstract

Power consumption of sensing circuitry in a NAND Flash device is reduced by reducing the voltage supply to a portion of logic circuits in sensing circuitry. A first power domain provides power to a first portion of the logic circuits in the sensing circuity and a second power domain provides power to a second portion of the logic circuits in the sensing circuitry. The first power domain has a higher voltage than the second power domain.


Find Patent Forward Citations

Quick Actions:

Cichocki, Mattia. (2025). Method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device (U.S. Patent No. 12315573). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12315573

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