The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2025
Filed:
May. 10, 2022
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Chun-Liang Tai, Hsinchu, TW;
Chun-Hsiang Fan, Hsinchu, TW;
Ta-Wei Lin, Hsinchu, TW;
Shih-Hsiang Chiu, New Taipei, TW;
Kuo-Bin Huang, Hsinchu County, TW;
Chieh-Chun Chiang, Taipei, TW;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Abstract
A method of manufacturing a semiconductor device is provided. The method comprises the following steps of forming a first semiconductor layer over a substrate, the first semiconductor layer comprising a first semiconductor material; etching the first semiconductor layer to form a first recess; forming a second semiconductor layer in the first recess, the second semiconductor layer comprising a second semiconductor material different from the first semiconductor material; etching the first semiconductor layer and the second semiconductor layer to form a first fin comprising the second semiconductor layer and the first semiconductor layer; forming an insulation material over the substrate, wherein a top surface of the insulation material is flush with a top surface of the first fin; performing an implantation process on the first fin to form an implant region near the top surface of the first fin; and partially removing the insulation material to form shallow trench isolation regions, wherein the first fin is sandwiched by two adjacent shallow trench isolation regions.