The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2025
Filed:
Jan. 06, 2023
Applicant:
International Business Machines Corporation, Armonk, NY (US);
Inventors:
Heng Wu, Santa Clara, CA (US);
Ruilong Xie, Niskayuna, NY (US);
Su Chen Fan, Cohoes, NY (US);
Jay William Strane, Warwick, NY (US);
Hemanth Jagannathan, Niskayuna, NY (US);
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/01 (2025.01); H01L 21/265 (2006.01); H10D 30/63 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01);
U.S. Cl.
CPC ...
H10D 84/017 (2025.01); H01L 21/265 (2013.01); H10D 30/63 (2025.01); H10D 62/116 (2025.01); H10D 64/021 (2025.01); H10D 84/0195 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01);
Abstract
A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.