The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 20, 2025
Filed:
Dec. 02, 2021
Applicant:
United Microelectronics Corp., Hsin-Chu, TW;
Inventors:
Chang-Po Hsiung, Hsinchu, TW;
Ching-Chung Yang, Hsinchu, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 64/01 (2025.01); H10D 64/27 (2025.01);
U.S. Cl.
CPC ...
H10D 64/513 (2025.01); H01L 21/02236 (2013.01); H01L 21/28211 (2013.01); H10D 30/022 (2025.01); H10D 30/601 (2025.01); H10D 64/017 (2025.01);
Abstract
A semiconductor device is disclosed. The semiconductor device includes a substrate, an active region in the substrate, a recessed region in the active region, a gate dielectric layer on the recessed region, a gate structure on the gate dielectric layer, and a source/drain region in the active region and at a side of the gate structure. An edge portion of the gate dielectric layer comprises a rounded profile, and the source/drain region directly contacts the edge portion of the gate dielectric layer.