The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Jun. 17, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Oreste Madia, Brussels, BE;

Georgios Vellianitis, Heverlee, BE;

Gerben Doornbos, Kessel-Lo, BE;

Marcus Johannes Henricus Van Dal, Linden, BE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); H10D 30/00 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6735 (2025.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6729 (2025.01); H10D 30/6755 (2025.01); H10D 30/6757 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/038 (2025.01); H10D 30/019 (2025.01); H10D 30/024 (2025.01); H10D 30/501 (2025.01); H10D 30/62 (2025.01);
Abstract

A method includes forming a first dielectric layer over a substrate; forming a first transistor over a first side of the first dielectric layer; removing the substrate to expose a second side of the first dielectric layer opposite to the first side of the second dielectric layer; and forming a second transistor over the second side of the first dielectric layer. Forming the first transistor includes forming a semiconductor layer over the first side of the first dielectric layer; forming a first gate structure over the semiconductor layer; and forming source/drain epitaxy structures on opposite sides of the first gate structure. Forming the second transistor includes forming a semiconductive oxide layer over the second side of the first dielectric layer; forming a second gate structure over the semiconductive oxide layer; and forming source/drain contacts over the semiconductive oxide layer and on opposite sides of the second gate structure.


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