The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Jan. 02, 2024
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Yu-Lien Huang, Jhubei, TW;

Guan-Ren Wang, Hsinchu, TW;

Ching-Feng Fu, Taichung, TW;

Yun-Min Chang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/62 (2025.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H10D 30/01 (2025.01); H10D 62/822 (2025.01); H10D 64/01 (2025.01); H01L 21/223 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H10D 62/00 (2025.01); H10D 62/13 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6211 (2025.01); H01L 21/0217 (2013.01); H01L 21/31116 (2013.01); H01L 21/32139 (2013.01); H01L 21/76802 (2013.01); H01L 21/7682 (2013.01); H01L 21/76877 (2013.01); H10D 30/024 (2025.01); H10D 30/6212 (2025.01); H10D 62/822 (2025.01); H10D 64/015 (2025.01); H10D 64/017 (2025.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/2236 (2013.01); H01L 21/26513 (2013.01); H01L 21/266 (2013.01); H10D 62/021 (2025.01); H10D 62/151 (2025.01); H10D 64/021 (2025.01);
Abstract

A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming source/drain regions over the fin on opposing sides of the gate structure; forming a first dielectric layer and a second dielectric layer successively over the source/drain regions; performing a first etching process to form an opening in the first dielectric layer and in the second dielectric layer, where the opening exposes an underlying electrically conductive feature; after performing the first etching process, performing a second etching process to enlarge a lower portion of the opening proximate to the substrate; and forming a contact plug in the opening after the second etching process.


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