The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Jun. 25, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Juan G. Alzate-Vinasco, Tigard, OR (US);

Travis W. LaJoie, Forest Grove, OR (US);

Wilfred Gomes, Portland, OR (US);

Fatih Hamzaoglu, Portland, OR (US);

Pulkit Jain, Hillsboro, OR (US);

James Waldemer, Hillsboro, OR (US);

Mark Armstrong, Portland, OR (US);

Bernhard Sell, Portland, OR (US);

Pei-Hua Wang, Hillsboro, OR (US);

Chieh-Jen Ku, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 12/00 (2023.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10B 12/315 (2023.02); H10B 12/0335 (2023.02); H10B 12/05 (2023.02); H10D 30/031 (2025.01); H10D 30/6728 (2025.01);
Abstract

A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.


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