The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Feb. 10, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Huai-Ying Huang, New Taipei, TW;

Yu-Ming Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 10/00 (2023.01); H01L 23/535 (2006.01); H01L 25/065 (2023.01); H10D 89/10 (2025.01);
U.S. Cl.
CPC ...
H10B 10/12 (2023.02); H01L 23/535 (2013.01); H01L 25/0657 (2013.01); H10B 10/18 (2023.02); H10D 89/10 (2025.01);
Abstract

A semiconductor device includes a semiconductor structure, a logic circuit, a plurality of first memory cells and through vias. The logic circuit is disposed at a first level over the semiconductor substrate. The first memory cells are disposed at a second level over the semiconductor substrate, wherein the second level is stacked on top and overlapped with the first level. Each of the first memory cells include a latch circuit and conductive elements. The latch circuit is formed of N-type field effect transistors (NFETs) and P-type field effect transistors (PFETs). The conductive elements are extending above the NFETs and the PFETs and electrically coupled to the NFETs and the PFETs. The through vias are extending from the second level to the first level and electrically connecting the conductive elements to the logic circuit by a vertical conduction path.


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