The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Jan. 30, 2023
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Kyle K. Kirby, Eagle, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/76897 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/10253 (2013.01);
Abstract

Systems and methods for multi-height interconnect structures for a semiconductor device are provided herein. The multi-height interconnect structure generally includes a primary level semiconductor die having a primary conductive pillar and a secondary conductive pillar, where the primary conductive pillar has a greater height than the secondary conductive pillar. The semiconductor device may further include a substrate electrically coupled to the primary level semiconductor die through the primary conductive pillar and a secondary level semiconductor die electrically coupled to the primary level semiconductor die through the secondary conductive pillar. The multi-height pillars may be formed using a single photoresist mask or multiple photoresist masks. In some configurations, the primary and secondary conductive pillars may be arranged on only the front-side of the dies and/or substrate.


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