The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 20, 2025

Filed:

Mar. 21, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Tomoharu Tanaka, Yokohama, JP;

Huai-Yuan Tseng, San Ramon, CA (US);

Dung V. Nguyen, San Jose, CA (US);

Kishore Kumar Muchherla, Fremont, CA (US);

Eric N. Lee, San Jose, CA (US);

Akira Goda, Tokyo, JP;

James Fitzpatrick, Laguna Niguel, CA (US);

Dave Ebsen, Minnetonka, MN (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0608 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01);
Abstract

A memory device includes an array of memory cells and a controller configured to access the array of memory cells. The controller is further configured to program a first number of bits to a first memory cell of the array of memory cells and program a second number of bits to a second memory cell of the array of memory cells. The controller is further configured to following a period after programming the second number of bits to the second memory cell, merge at least a subset of the first number of bits stored in the first memory cell to the second number of bits stored in the second memory cell without erasing the second memory cell such that the second number of bits plus at least the subset of the first number of bits are stored in the second memory cell.


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