The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Dec. 05, 2023
Applicants:

Etron Technology, Inc., Hsinchu, TW;

Invention and Collaboration Laboratory Pte. Ltd., Singapore, SG;

Inventor:

Chao-Chun Lu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/04 (2006.01); G11C 5/02 (2006.01); H01L 25/065 (2023.01); H10B 12/00 (2023.01); H10D 88/00 (2025.01);
U.S. Cl.
CPC ...
H10B 12/36 (2023.02); G11C 5/025 (2013.01); H01L 25/0657 (2013.01); H10D 88/00 (2025.01);
Abstract

An IC system includes a package, a plurality of memory dies, and a logic chip. The plurality of memory dies are within the package, each memory die includes a memory region and abridge area, the memory region of each memory die includes a plurality of memory cells and each memory cell includes a first transistor, and the bridge area of each memory die includes a plurality of memory input/output (I/O) pads and a plurality of third transistors. The logic chip includes a logic bridge area and a plurality of second transistors, and the logic bridge area includes a plurality of logic I/O pads. Each memory die is horizontally spaced apart from the logic chip, and the plurality of memory I/O pads of each memory die are electrically coupled to the plurality of logic I/O pads. Each memory die is horizontally spaced apart from each other.


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