The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Feb. 28, 2024
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ebony L. Mays, Hillsboro, OR (US);

Bruce J. Tufts, Banks, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/76 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/02271 (2013.01); H01L 21/0228 (2013.01); H01L 21/02282 (2013.01); H01L 29/0649 (2013.01);
Abstract

Disclosed herein are methods for manufacturing IC components using bottom-up fill of openings with a dielectric material. In one aspect, an exemplary method includes, first, depositing a solid dielectric liner on the inner surfaces of the openings using a non-flowable process, and subsequently filling the remaining empty volume of the openings with a fill dielectric using a flowable process. Such a combination method may maximize the individual strengths of the non-flowable and flowable processes due to the synergetic effect achieved by their combined use, while reducing their respective drawbacks. Assemblies and devices manufactured using such methods are disclosed as well.


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