The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 13, 2025

Filed:

Aug. 05, 2022
Applicant:

Kepler Computing Inc., San Francisco, CA (US);

Inventors:

Rajeev Kumar Dokania, Beaverton, OR (US);

Mustansir Yunus Mukadam, Seattle, WA (US);

Noriyuki Sato, Hillsboro, OR (US);

Tanay Gosavi, Portland, OR (US);

Niloy Mukherjee, San Ramon, CA (US);

Amrita Mathuriya, Portland, OR (US);

Sasikanth Manipatruni, Portland, OR (US);

Assignee:

Kepler Computing Inc., San Francisco, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
G11C 11/2255 (2013.01); G11C 11/221 (2013.01); G11C 11/2257 (2013.01);
Abstract

A memory is described having a plurality of bit-cells organized in a row or column. An individual bit-cell of the plurality of bit-cells includes an access transistor and a plurality of capacitors. A word-line is positioned under the access transistor, wherein the access transistor is controllable by the word-line, whereas the plurality of capacitors is positioned above the access transistor. The individual bit-cell has an individual boundary which substantially abuts a neighboring bit-cell in the row or column such that there is no dummy bit-cell between individual bit-cell and the neighboring bit-cell.


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