The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 06, 2025
Filed:
Dec. 04, 2021
Yibu Semiconductor Co., Ltd., Shanghai, CN;
Weiping Li, Shanghai, CN;
Yibu Semiconductor Co., Ltd., Shanghai, CN;
Abstract
The present application provides a method for forming chip packages and a chip package. The method comprises arranging a plurality of interconnect devices at intervals on a surface of a carrier and assembling a plurality of chipsets over the interconnect devices. Each chipset comprises at least two chips electrically connected through an interconnect device. A front surface of each chip facing the carrier is provided with a plurality of first bumps. The method further comprises forming a molded package layer whereby the plurality of chipsets and the plurality of interconnect devices are embedded in the molded package layer; removing the carrier and thinning the molded package layer to expose the first bumps; forming second bumps on the surface on one side of the molded package layer where the first bumps are exposed; and dicing the molded package layer to obtain a plurality of package units. Thus, a flexible and low-cost packaging scheme is provided for multi-chip interconnection.