The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

Apr. 01, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ming-Yang Huang, Kaohsiung, TW;

Yung Feng Chang, Hsinchu, TW;

Tung-Heng Hsieh, Hsinchu County, TW;

Bao-Ru Young, Hsinchu County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2005.12); H01L 21/8238 (2005.12); H01L 27/092 (2005.12);
U.S. Cl.
CPC ...
H01L 27/0207 (2012.12); H01L 21/823842 (2012.12); H01L 27/092 (2012.12); H01L 27/0924 (2012.12); H01L 21/823821 (2012.12); H01L 21/823857 (2012.12);
Abstract

An IC includes a first standard cell (SC) having a first circuit area (CA) and a first transition area (TA) placed on an edge of the CA; and a SChaving a CAand a TAplaced on an edge of CA'. CAincludes a first and a second active region (ARand AR) longitudinally oriented along a first direction (D), and a first gate stack (G) along a D⊥Dand extending over ARand AR. Gincludes a first gate segment (GS) contacting ARand a GScontacting AR. GSand GSare different in composition. GSand GSare associated with a pFET and a nFET, respectively. TAincludes a Glongitudinally oriented along Dand spans between opposite cell edges of the SC. Gis a lengthwise uniform gate stack. SCis placed in abutment with the SCsuch that TAand TAshare a common edge.


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