The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

Mar. 21, 2022
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Junwoo Park, Asan-si, KR;

Seunghwan Kim, Asan-si, KR;

Jungjoo Kim, Daegu, KR;

Yongkwan Lee, Gyeonggi-do, KR;

Dongju Jang, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2005.12); H01L 23/00 (2005.12); H01L 23/31 (2005.12);
U.S. Cl.
CPC ...
H01L 23/49833 (2012.12); H01L 23/3128 (2012.12); H01L 24/16 (2012.12); H01L 24/32 (2012.12); H01L 24/73 (2012.12); H01L 2224/16227 (2012.12); H01L 2224/16235 (2012.12); H01L 2224/32225 (2012.12); H01L 2224/73204 (2012.12);
Abstract

A semiconductor package includes a lower substrate that includes a lower wiring layer; a semiconductor chip disposed on the lower substrate, and an upper substrate disposed on the semiconductor chip. The upper substrate includes a lower surface that faces the semiconductor chip, an upper wiring layer, and a plurality of protruding structures disposed below the lower surface. The lower surface of the upper substrate includes a cavity region that overlaps the semiconductor chip in a first direction, and a plurality of channel regions that extend from the cavity region to an edge of the upper substrate. The cavity region and the plurality of channel regions are defined by the plurality of protruding structures.


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