The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

Jun. 06, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Min-Feng Ku, Hsinchu, TW;

Yao-Chun Chuang, Hsinchu, TW;

Cheng-Chien Li, Hsinchu County, TW;

Ching-Pin Lin, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2005.12); H01L 21/768 (2005.12); H01L 23/522 (2005.12); H01L 23/528 (2005.12); H01L 23/538 (2005.12); H01L 23/58 (2005.12);
U.S. Cl.
CPC ...
H01L 23/481 (2012.12); H01L 21/76816 (2012.12); H01L 21/76877 (2012.12); H01L 21/76898 (2012.12); H01L 23/5226 (2012.12); H01L 23/528 (2012.12); H01L 23/5389 (2012.12); H01L 23/585 (2012.12);
Abstract

An exemplary semiconductor structure includes a device substrate having a first side and a second side. A dielectric layer is disposed over the first side of the device substrate. A through via extends along a first direction through the dielectric layer and through the device substrate from the first side to the second side. The through via has a total length along the first direction and a width along a second direction that is different than the first direction. The total length is a sum of a first length of the through via in the dielectric layer and a second length of the through via in the device substrate. The first length is less than the second length. A guard ring is disposed in the dielectric layer and around the through via.


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