The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

May. 11, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Chi-Wei Wu, Hsinchu, TW;

Hsin-Che Chiang, Taipei, TW;

Chun-Sheng Liang, Changhua County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2005.12); H01L 21/762 (2005.12); H01L 27/092 (2005.12);
U.S. Cl.
CPC ...
H01L 21/823878 (2012.12); H01L 21/76232 (2012.12); H01L 21/823814 (2012.12); H01L 21/823821 (2012.12); H01L 21/823871 (2012.12); H01L 27/0924 (2012.12);
Abstract

A method includes forming first and second gate stacks extending across a semiconductor fin on a substrate; forming source/drain regions in the semiconductor fin, wherein one of the source/drain region is between the first and second gate stacks; forming a dielectric layer laterally surrounding the first and second gate stacks; doping a portion of the dielectric layer between the first and second gate stacks with a dopant; removing the second gate stack to form a gate trench next to the doped first portion of the dielectric layer; performing an annealing process to expand the doped first portion of the dielectric layer toward the gate trench; forming an isolation structure in the gate trench and next to the expanded first portion of the dielectric layer; forming a source/drain contact extending through the dielectric layer to the one of the source/drain regions.


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