The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 29, 2025

Filed:

Mar. 27, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jonathan Combs, Austin, TX (US);

Michael Chynoweth, Placitas, NM (US);

Beeman Strong, Portland, OR (US);

Charlie Hewett, Bellevue, WA (US);

Patrick Konsor, Hillsboro, OR (US);

Vidisha Chirra, Austin, TX (US);

Asavari Paranjape, Austin, TX (US);

Ahmad Yasin, Haifa, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/34 (2005.12); G06F 9/38 (2017.12); G06F 11/30 (2005.12); G06F 12/0802 (2015.12); G06F 17/40 (2005.12);
U.S. Cl.
CPC ...
G06F 9/3804 (2012.12); G06F 11/3024 (2012.12); G06F 11/3495 (2012.12); G06F 12/0802 (2012.12); G06F 2212/30 (2012.12);
Abstract

Systems, methods, and apparatuses relating to circuitry to implement precise last branch record event logging in a processor are described. In one embodiment, a hardware processor core includes an execution circuit to execute instructions, a retirement circuit to retire executed instructions, a status register, and a last branch record circuit to, in response to retirement by the retirement circuit of a first taken branch instruction, start a cycle timer and a performance monitoring event counter, and in response to retirement by the retirement circuit of a second taken branch instruction, that is a next taken branch instruction in program order after the first taken branch instruction, write values from the cycle timer and the performance monitoring event counter into a first entry in the status register and clear the values from the cycle timer and the performance monitoring event counter.


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