The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Mar. 08, 2022
Applicant:

Via Labs, Inc., New Taipei, TW;

Inventor:

Sheng-Yuan Lee, New Taipei, TW;

Assignee:

VIA LABS, INC., New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2005.12); H01F 17/00 (2005.12); H10D 1/20 (2024.12);
U.S. Cl.
CPC ...
H10D 1/20 (2024.12); H01F 17/0013 (2012.12); H01L 23/5227 (2012.12); H01F 2017/0086 (2012.12);
Abstract

A multilayer-type on-chip inductor includes a first winding portion arranged in an inter-metal dielectric (IMD) layer, which includes first and second semi-circular stacking layers arranged from inside to outside and in concentricity. A second winding portion includes third and fourth semi-circular stacking layers arranged symmetrically with the first semi-circular stacking layer and the second semi-circular stacking layer, respectively, with respect to a symmetry axis. A conductive branch layer is disposed in an insulating redistribution layer over the IMD layer. The first, second, third, and fourth semi-circular stacking layers each include an uppermost trace layer and a next uppermost trace layer vertically stacked under the uppermost trace layer.


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