The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2025
Filed:
Mar. 30, 2022
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/16 (2022.12); H01L 21/48 (2005.12); H01L 23/00 (2005.12); H01L 23/48 (2005.12); H01L 23/498 (2005.12);
U.S. Cl.
CPC ...
H01L 25/162 (2012.12); H01L 21/4853 (2012.12); H01L 21/4857 (2012.12); H01L 23/481 (2012.12); H01L 23/49811 (2012.12); H01L 23/49822 (2012.12); H01L 23/49838 (2012.12); H01L 24/16 (2012.12); H01L 24/32 (2012.12); H01L 24/33 (2012.12); H01L 24/73 (2012.12); H01L 25/165 (2012.12); H01L 24/48 (2012.12); H01L 2224/16227 (2012.12); H01L 2224/16237 (2012.12); H01L 2224/3201 (2012.12); H01L 2224/32059 (2012.12); H01L 2224/32145 (2012.12); H01L 2224/32225 (2012.12); H01L 2224/32265 (2012.12); H01L 2224/3303 (2012.12); H01L 2224/33051 (2012.12); H01L 2224/33181 (2012.12); H01L 2224/48228 (2012.12); H01L 2224/73204 (2012.12); H01L 2224/73253 (2012.12); H01L 2224/73265 (2012.12); H01L 2924/1431 (2012.12); H01L 2924/1434 (2012.12); H01L 2924/3511 (2012.12);
Abstract
A semiconductor package includes; a substrate including a first insulating layer and a first conductive pattern in the first insulating layer, a first semiconductor chip on the substrate, an interposer spaced apart from the first semiconductor chip in a direction perpendicular to an upper surface of the substrate and including a second insulating layer and a second conductive pattern in the second insulating layer, a first element between the first semiconductor chip and the interposer, a connection member between the substrate and the interposer, and a mold layer covering side surfaces of the first semiconductor chip and side surfaces of the first element.