The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

May. 09, 2022
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Marcus Boehm, Thalmassing, DE;

Michael Fuegl, Neumarkt, DE;

Ludwig Heitzer, Falkenfels, DE;

Stefan Woetzel, Erfurt, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2005.12); H01L 21/48 (2005.12); H01L 21/56 (2005.12); H01L 23/31 (2005.12);
U.S. Cl.
CPC ...
H01L 23/49506 (2012.12); H01L 21/4825 (2012.12); H01L 21/565 (2012.12); H01L 23/3107 (2012.12); H01L 23/3135 (2012.12); H01L 23/49524 (2012.12); H01L 23/49562 (2012.12); H01L 23/49568 (2012.12);
Abstract

A molded semiconductor package includes: a mold compound; a metal substrate partly embedded in the mold compound; at least one first metal lead partly embedded in the mold compound; an inlay embedded in the mold compound, the inlay comprising a semiconductor die embedded in an electrically insulating body, a first metal structure attached to a first side of the semiconductor die, and a second metal structure attached to a second side of the semiconductor die; and a metal clip at least partly embedded in the mold compound and connecting the second metal structure to the at least one first metal lead. The semiconductor die has a maximum junction temperature higher than a glass transition temperature of the mold compound, the electrically insulating body has a glass transition temperature at or above the maximum junction temperature of the semiconductor die, and the metal substrate is attached to the first metal structure.


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