The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Sep. 08, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Gongyi Wu, Hefei, CN;

Yong Lu, Hefei, CN;

Youquan Yu, Hefei, CN;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2005.12); H01L 21/3105 (2005.12); H01L 21/768 (2005.12); H01L 29/06 (2005.12); H10D 62/10 (2024.12);
U.S. Cl.
CPC ...
H01L 21/76229 (2012.12); H01L 21/31053 (2012.12); H01L 21/7681 (2012.12); H10D 62/115 (2024.12);
Abstract

A semiconductor device manufacturing method includes: providing a semiconductor substrate, wherein the semiconductor substrate includes an array region and a peripheral region; word line structures and shallow trench isolation structures are formed in the array region, grooves are formed over word line structures, and a shallow trench isolation structure is formed in the peripheral region; depositing at least two insulating layers on a surface of the semiconductor substrate, each of the insulating layer has a different etch rate under a same etching condition; and removing part of the insulating layers located on surfaces of the array region and the peripheral region in sequence, wherein a lower insulating layer in the adjacent insulating layers is an etch stop layer of an upper insulating layer, and keeping all the insulating layers in the grooves located over the word line structures.


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