The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Dec. 20, 2023
Applicant:

Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US);

Inventors:

Gaius Gillman Fountain, Jr., Youngsville, NC (US);

Belgacem Haba, Saratoga, CA (US);

George Carlton Hudson, Wendell, NC (US);

Pawel Mrozek, San Jose, CA (US);

Suhail Jaan Sadiq, Dublin, CA (US);

Laura Mirkarimi, Sunol, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2005.12); H01L 23/467 (2005.12); H01L 23/473 (2005.12);
U.S. Cl.
CPC ...
H01L 21/4882 (2012.12); H01L 23/467 (2012.12); H01L 23/473 (2012.12);
Abstract

A method of manufacturing a device package. The method comprises patterning a first substrate to form patterned regions comprising a thermal oxide layer. The method further comprises directly bonding the patterned regions of the first substrate to a second substrate to form a bonding interface. The bonded first and second substrates form an integrated cooling assembly comprising a coolant chamber volume. Portions of the first substrate exposed to the coolant chamber volume comprise a native oxide layer.


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