The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 21, 2025
Filed:
Jun. 09, 2022
Applicant:
Sandisk Technologies Llc, Addison, TX (US);
Assignee:
Sandisk Technologies, Inc., Milpitas, CA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2005.12); G11C 11/56 (2005.12); G11C 16/04 (2005.12); G11C 16/16 (2005.12); H01L 23/00 (2005.12); H01L 25/065 (2022.12); H01L 25/18 (2022.12);
U.S. Cl.
CPC ...
G11C 16/10 (2012.12); G11C 11/5628 (2012.12); G11C 11/5635 (2012.12); G11C 11/5671 (2012.12); G11C 16/0483 (2012.12); G11C 16/16 (2012.12); H01L 24/08 (2012.12); H01L 25/0657 (2012.12); H01L 25/18 (2012.12); H01L 2224/08145 (2012.12); H01L 2924/1431 (2012.12); H01L 2924/14511 (2012.12);
Abstract
The memory device that includes a die with a CMOS wafer with programming and erasing circuitry. The die also includes a plurality of array wafers coupled with and in electrical communication with the CMOS wafer and having different programming and erasing efficiencies. Each of the array wafers includes memory blocks with memory cells. The control circuitry of the CMOS wafer is configured to output at least one of different initial programming voltages and unique erase voltages to the plurality of array wafers.