Macro-op cache data entry pointers distributed as initial pointers held in tag array and next pointers held in data array for efficient and performant variable length macro-op cache entries

Abstract

A microprocessor includes a macro-op (MOP) cache (MOC) comprising a set-associative MOC tag RAM (MTR) and a MOC data RAM (MDR) managed as a pool of MDR entries. A MOC entry (ME) comprises one MTR entry and one or more MDR entries that hold the MOPs of the ME. The MDR entries of the ME have a program order. Each MDR entry holds MOPs and a next MDR entry pointer. Each MTR entry holds initial MDR entry pointers and specifies the number of the MDR entries of the ME. During ME allocation, the MOC populates the MDR entry pointers to point to the MDR entries based on the program order. In response to an access that hits upon an MTR entry, the MOC fetches the MDR entries according to the program order initially using the initial pointers and subsequently using the next pointers.