The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 21, 2025

Filed:

Jun. 21, 2022
Applicant:

Globalfoundries U.s. Inc., Malta, NY (US);

Inventors:

Siva P. Adusumilli, South Burlington, VT (US);

Mark D. Levy, Williston, VT (US);

Ramsey M. Hazbun, Colchester, VT (US);

John J. Ellis-Monaghan, Grand Isle, VT (US);

Assignee:

GlobalFoundries U.S. Inc., Malta, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01N 27/06 (2005.12); H10F 30/223 (2024.12); H10F 71/00 (2024.12); H10F 77/14 (2024.12);
U.S. Cl.
CPC ...
G01N 27/06 (2012.12); H10F 30/223 (2024.12); H10F 71/121 (2024.12); H10F 77/143 (2024.12);
Abstract

Disclosed is a semiconductor structure with a photodiode including: a well region with a first-type conductivity in a substrate, a trench in the well region, and multiple conformal semiconductor layers in the trench. The semiconductor layers include a first semiconductor layer, which is, for example, an intrinsic semiconductor layer and lines the trench, and a second semiconductor layer, which has a second-type conductivity and which is on the first semiconductor layer within (but not filling) the trench and which also extends outside the trench onto a dielectric layer. An additional dielectric layer extends over and caps a cavity that is at least partially within the trench such that surfaces of the second semiconductor layer are exposed within the cavity. Fluid inlet/outlet ports extend to the cavity and contacts extend to the well region and to the second semiconductor layer. Also disclosed are methods for forming and using the semiconductor structure.


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