The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Dec. 26, 2021
Applicant:

Sandisk Technologies Llc, San Jose, CA (US);

Inventors:

Srinivas Pulugurtha, San Jose, CA (US);

Yanli Zhang, San Jose, CA (US);

Johann Alsmeier, San Jose, CA (US);

Mitsuhiro Togo, Yokkaichi, JP;

Assignee:

Sandisk Technologies, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/00 (2024.12); H10D 30/01 (2024.12); H10D 30/62 (2024.12); H10D 64/27 (2024.12);
U.S. Cl.
CPC ...
H10D 30/6211 (2024.12); H10D 30/024 (2024.12); H10D 64/513 (2024.12);
Abstract

A semiconductor structure includes a semiconductor substrate containing a shallow trench isolation structure that laterally surrounds a transistor active region, at least one line trench vertically extending into the semiconductor substrate, and a source region and a drain region located in the transistor active region. A contoured channel region continuously extends from the source region to the drain region underneath the at least one line trench. A gate dielectric contacts all surfaces of the at least one line trench and extends over an entirety of the contoured channel region. A gate electrode containing at least one fin portion overlies the gate dielectric.


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