The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Feb. 22, 2024
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Marco Sforzin, Cernusco sul Naviglio, IT;

Paolo Amato, Treviglio, IT;

Innocenzo Tortorelli, Cernusco sul Naviglio, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2005.12); G11C 29/02 (2005.12); G11C 29/12 (2005.12);
U.S. Cl.
CPC ...
G11C 13/0033 (2012.12); G11C 13/0004 (2012.12); G11C 13/0038 (2012.12); G11C 13/004 (2012.12); G11C 13/0069 (2012.12); G11C 29/021 (2012.12); G11C 29/12005 (2012.12);
Abstract

A memory device can include a plurality of memory cells including a first group of memory cells and a second group of memory cells programmed to a predefined logic state. The plurality of memory cells includes a memory controller configured to apply a reading voltage to at least one selected memory cell of the first group during a reading operation, apply the reading voltage to the memory cells of the second group, and responsive to the logic state of at least one memory cell of the second group being assessed to be different from the predefined logic state perform a refresh operation of the memory cells of the first group by applying a recovery voltage higher than the reading voltage to assess the logic state thereof and reprogramming the memory cells of the first group to the logic state assessed with the recovery voltage.


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