The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 14, 2025

Filed:

Apr. 13, 2022
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Peter Wohl, Williston, VT (US);

John A. Waicukauski, Tualatin, OR (US);

Assignee:

Synopsys, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3308 (2019.12); G06F 30/20 (2019.12); G06F 30/367 (2019.12); G06F 30/396 (2019.12); G06F 30/398 (2019.12);
U.S. Cl.
CPC ...
G06F 30/3308 (2019.12); G06F 30/20 (2019.12); G06F 30/367 (2019.12); G06F 30/396 (2019.12); G06F 30/398 (2019.12);
Abstract

A system and method generates test patterns for simulating a circuit design. Generating the test patterns includes determining clock data of the circuit design. The clock data is determined by determining a first clock signal pair from clock signals, and determining a disturb cell based on the first clock signal pair. The disturb cell is electrically coupled to a first clock signal of the first clock signal pair, and to a second cell. The second cell is electrically coupled to a second clock signal of the first clock signal pair, and an input of the second cell is electrically coupled to an output of the disturb cell. A first test pattern is generated based on the clock data and is output to a memory to be used in simulating a circuit design.


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