The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Oct. 04, 2022
Applicant:

Adeia Semiconductor Technologies Llc, San Jose, CA (US);

Inventors:

Belgacem Haba, Saratoga, CA (US);

Arkalgud R. Sitaram, Cupertino, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 23/00 (2006.01); H01L 23/64 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 21/02164 (2013.01); H01L 21/02181 (2013.01); H01L 21/0228 (2013.01); H01L 21/31111 (2013.01); H01L 23/642 (2013.01); H01L 24/27 (2013.01); H01L 24/32 (2013.01); H01L 24/83 (2013.01); H01L 25/50 (2013.01); H01L 2224/08121 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/27452 (2013.01); H01L 2224/27614 (2013.01); H01L 2224/29187 (2013.01); H01L 2224/32135 (2013.01); H01L 2224/80 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2224/83896 (2013.01); H01L 2225/06531 (2013.01); H01L 2924/01072 (2013.01); H01L 2924/0534 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/14 (2013.01); H01L 2924/30105 (2013.01);
Abstract

Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.


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