The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2025

Filed:

Sep. 22, 2021
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventor:

Robert D. Clark, Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/78 (2006.01); H01L 21/306 (2006.01); H01L 21/311 (2006.01); H10D 86/01 (2025.01);
U.S. Cl.
CPC ...
H01L 21/7806 (2013.01); H01L 21/30621 (2013.01); H01L 21/31116 (2013.01); H10D 86/0214 (2025.01);
Abstract

A backside reveal method includes providing a semiconductor material substrate, depositing an epitaxial high-k etch stop layer on the semiconductor material substrate, forming an integrated circuit device layer on the epitaxial high-k etch stop layer, and attaching a carrier substrate to a front side of the integrated circuit device layer. The method further includes removing a portion of a thickness of the semiconductor material substrate to leave a remaining portion of the thickness of the semiconductor material substrate, removing, by a first selective etching, the remaining portion of the semiconductor material substrate, and removing, by a second selective etching, the epitaxial high-k etch stop layer to expose a backside of the integrated circuit device layer. The epitaxial high-k etch stop layer has good lattice match and high etch selectivity relative to the semiconductor material substrate.


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