The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 08, 2025
Filed:
Aug. 15, 2022
Micron Technology, Inc., Boise, ID (US);
Andrea Giovanni Xotta, Avezzano, IT;
Dheeraj Srinivasan, San Jose, CA (US);
Ali Mohammadzadeh, Mountain View, CA (US);
Karl D. Schuh, Santa Cruz, CA (US);
Guido Luciano Rizzo, Avezzano, IT;
Jung Sheng Hoei, Newark, CA (US);
Michele Piccardi, Cupertino, CA (US);
Tommaso Vali, Sezze, IT;
Umberto Siciliani, Rubano, IT;
Rohitkumar Makhija, Milpitas, CA (US);
June Lee, Sunnyvale, CA (US);
Aaron S. Yip, Los Gatos, CA (US);
Daniel J. Hubbard, Boise, ID (US);
Micron Technology, Inc., Boise, ID (US);
Abstract
A memory device includes a memory array comprising a plurality of memory planes, wherein the plurality of memory planes are arranged in a plurality of independent plane groups, and wherein each of the plurality of independent plane groups comprises one or more of the plurality of memory planes. The memory device further includes a plurality of independent analog driver circuits coupled to the memory array, wherein a respective one of the plurality of independent analog driver circuits is associated with a respective one of the plurality of independent plane groups. The memory device further includes a common analog circuit coupled to the memory array, wherein the common analog circuit is shared by the plurality of independent analog driver circuits and the plurality of independent plane groups. The memory device further includes a plurality of control logic elements, wherein a respective one of the plurality of control logic elements is associated with a respective one of the plurality of independent analog driver circuits and a respective one of the plurality of independent plane groups.