The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Jun. 13, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Yen-Ku Lin, Zhubei, TW;

Ru-Yi Su, Kouhu Township, TW;

Haw-Yun Wu, Zhubei, TW;

Chun-Lin Tsai, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/00 (2006.01); H01L 25/07 (2006.01); H02M 1/00 (2007.01); H02M 1/42 (2007.01); H02M 3/335 (2006.01); H02M 7/00 (2006.01); H02M 7/219 (2006.01);
U.S. Cl.
CPC ...
H02M 3/003 (2021.05); H01L 25/074 (2013.01); H02M 1/007 (2021.05); H02M 1/4233 (2013.01); H02M 3/01 (2021.05); H02M 3/33571 (2021.05); H02M 7/003 (2013.01); H02M 7/219 (2013.01);
Abstract

Bonding a full-bridge device and an LLC device in a stack, or forming the full-bridge device and the LLC device on a same substrate, rather than connecting the devices, reduces a chip area associated with a power converter including the full-bridge device and the LLC device. Additionally, the full-bridge device and the LLC device consume less power because parasitic inductance and capacitance are reduced. Additionally, raw materials and production time are conserved that would otherwise have been used to connect the full-bridge device and the LLC device (e.g., via wires).


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