The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Jul. 19, 2023
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Mrunal A. Khaderbad, Hsinchu, TW;

Pang-Yen Tsai, Jhubei, TW;

Yasutoshi Okuno, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/45 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/45 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823871 (2013.01); H01L 27/0924 (2013.01); H01L 29/41791 (2013.01);
Abstract

A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.


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