The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 01, 2025

Filed:

Aug. 13, 2021
Applicant:

Changxin Memory Technologies, Inc., Hefei, CN;

Inventors:

Yong Lu, Hefei, CN;

Gongyi Wu, Hefei, CN;

Hongkun Shen, Hefei, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01G 4/06 (2006.01); H01G 4/008 (2006.01); H01G 4/012 (2006.01); H01G 4/12 (2006.01); H01G 4/33 (2006.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01);
U.S. Cl.
CPC ...
H01L 28/60 (2013.01); H01G 4/008 (2013.01); H01G 4/012 (2013.01); H01G 4/06 (2013.01); H01G 4/1272 (2013.01); H01G 4/33 (2013.01); H01L 28/90 (2013.01); H10B 12/03 (2023.02); H10B 12/30 (2023.02); H01G 4/1218 (2013.01); H01G 4/1236 (2013.01); H10B 12/033 (2023.02);
Abstract

A capacitor structure and a method of manufacturing the same, and a memory are provided. The method includes the following operations. A substrate is provided. A first conductive structure with a shape of column is formed on the substrate. A second conductive structure is formed on the substrate. The second conductive structure surrounds the first conductive structure and is spaced with the first conductive structure. The first conductive structure and the second conductive structure together form a bottom electrode. A capacitor dielectric layer is formed. The capacitor dielectric layer covers the surface of the substrate and the surface of the bottom electrode. A top electrode covering the surface of the capacitor dielectric layer is formed.


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