The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2025
Filed:
Apr. 07, 2022
Applied Materials, Inc., Santa Clara, CA (US);
Andrew Anthony Cockburn, Brabant-Wallon, BE;
Vanessa Pena, Leuven, BE;
Daniel Philippe Cellier, Wallonia, BE;
John Tolle, Gilbert, AZ (US);
Thomas Kirschenheiter, Tempe, AZ (US);
Wei Hong, Dublin, CA (US);
Ellie Y. Yieh, San Jose, CA (US);
Mehul Naik, San Jose, CA (US);
Seshadri Ramaswami, Santa Clara, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Abstract
Embodiments of the disclosure advantageously provide semiconductor devices CFET in particular and methods of manufacturing such devices having a fully strained superlattice structure with channel layers that are substantially free of defects and release layers having a reduced selective removal rate. The CFET described herein comprise a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of from greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprise alternating layers of nanosheet channel layer that comprise silicon (Si) and nanosheet release layer that comprise doped silicon germanium (SiGe).