The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Jul. 25, 2022
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shih-Yao Lin, New Taipei, TW;

Kuei-Yu Kao, Hsinchu, TW;

Chen-Ping Chen, Toucheng Township, TW;

Chih-Han Lin, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 21/762 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/0273 (2013.01); H01L 21/31144 (2013.01); H01L 21/76224 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823456 (2013.01); H01L 21/823462 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/1037 (2013.01); H01L 29/42364 (2013.01); H01L 29/42376 (2013.01); H01L 29/42392 (2013.01); H01L 29/513 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/66553 (2013.01); H01L 29/6656 (2013.01);
Abstract

A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.


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