The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 25, 2025

Filed:

Mar. 12, 2024
Applicant:

Fujian Jinhua Integrated Circuit Co., Ltd., Jinjiang, CN;

Inventors:

Yi-Wang Jhan, Jinjiang, CN;

Yung-Tai Huang, Jinjiang, CN;

Xin You, Jinjiang, CN;

Xiaopei Fang, Jinjiang, CN;

Yu-Cheng Tung, Jinjiang, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H10D 30/01 (2025.01); H10D 62/17 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/03 (2013.01); H10D 30/027 (2025.01); H10D 62/235 (2025.01); H10D 64/258 (2025.01); H10D 84/0144 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01); H01L 2224/036 (2013.01); H01L 2224/0508 (2013.01); H01L 2224/05099 (2013.01);
Abstract

A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a plurality of gate conductive patterns on the substrate; an interlayer dielectric layer covering the gate conductive patterns on the substrate; an interconnect structure comprising a contact plug and a first contact pad, the contact plug extending through the interlayer dielectric layer to the substrate, the first contact pad fully covering a top of the contact plug and extending laterally over part of a top surface of the interlayer dielectric layer; and a second contact pad formed on the top surface of the interlayer dielectric layer and spaced apart from a side edge of the first contact pad, wherein the second contact pad is formed and fully overlays on the interlayer dielectric layer and an isolation plug is spaced apart from the first contact pad.


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