The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Nov. 20, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Nuo Xu, Milpitas, CA (US);

Sai-Hooi Yeong, Hsinchu County, TW;

Yu-Ming Lin, Hsinchu, TW;

Zhiqiang Wu, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); G11C 11/22 (2006.01); G11C 16/04 (2006.01); H01L 27/06 (2006.01); H01L 29/66 (2006.01); H10B 51/00 (2023.01); H10B 51/30 (2023.01);
U.S. Cl.
CPC ...
H10B 51/30 (2023.02); G11C 11/223 (2013.01); G11C 16/0466 (2013.01); G11C 16/0483 (2013.01); H01L 27/0688 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H10B 51/00 (2023.02);
Abstract

A method for forming a semiconductor memory structure includes following operations. A plurality of doped regions are formed in a semiconductor substrate. The doped regions are separated from each other. A stack including a plurality of first insulating layers and a plurality of second insulating layers alternately arranged is formed over the semiconductor substrate. A first trench is formed in the stack. The second insulating layers are replaced with a plurality of conductive layers. A second trench is formed. A charge-trapping layer and a channel layer are formed in the second trench. An isolation structure is formed to fill the second trench. A source structure and a drain structure are formed at two sides of the isolation structure.


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