The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Feb. 23, 2023
Applicant:

Yangtze Memory Technologies Co., Ltd., Hubei, CN;

Inventors:

Yan Wang, Hubei, CN;

Xiaojiang Guo, Hubei, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/12 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1039 (2013.01); G11C 7/106 (2013.01); G11C 7/12 (2013.01);
Abstract

The present disclosure provides a memory device that includes a memory array and a page buffer. The memory array includes a plurality of memory cells coupled to a bit line of the memory array. The page buffer is coupled to the plurality of memory cells via the bit line to sense stored data in the memory cells. The page buffer includes first, second, and third transistors coupled to the bit line, first and second nodes, a capacitance structure coupled to the first node, and a latch circuit coupled to the bit line via the first transistor. First terminals of the first, second, and third transistors are coupled to the first node. A second terminal of the second transistor is coupled to the second node. The third transistor amplifies a read margin voltage at the second node. The page buffer shortens a time of a read operation or verify operation.


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