The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 18, 2025
Filed:
May. 09, 2023
Applicant:
Macronix International Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
MACRONIX International Co., Ltd., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 5/06 (2006.01); G11C 7/06 (2006.01); G11C 16/08 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H10B 41/20 (2023.01); H10B 41/40 (2023.01); H10B 43/20 (2023.01); H10B 43/40 (2023.01); H10B 80/00 (2023.01);
U.S. Cl.
CPC ...
G11C 7/06 (2013.01); G11C 5/063 (2013.01); G11C 16/08 (2013.01); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 25/0657 (2013.01); H10B 41/20 (2023.02); H10B 41/40 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02); H10B 80/00 (2023.02); H01L 2224/0556 (2013.01); H01L 2224/16146 (2013.01); H01L 2225/06541 (2013.01);
Abstract
A memory device, such as a three-dimensional AND or NOR flash memory, includes a first chip and a second chip. The first chip has multiple source line switches, multiple bit line switches, multiple page buffers, and multiple sensing amplifiers. The first chip has multiple first pads. The second chip has multiple memory cells to form multiple memory cell blocks. Multiple second pads are on a first surface of the second chip to be respectively coupled to multiple local bit lines and multiple local source lines of the memory cell blocks. Each of the first pads is coupled to the corresponding second pads.