The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 18, 2025

Filed:

Aug. 31, 2023
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Dai-Ying Lee, Hsinchu County, TW;

Teng-Hao Yeh, Zhubei, TW;

Wei-Chen Chen, Taoyuan, TW;

Rachit Dobhal, New Taipei, TW;

Zefu Zhao, Taipei, TW;

Chee-Wee Liu, Taipei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); G11C 5/06 (2006.01); H10B 51/20 (2023.01); H10D 30/01 (2025.01); H10D 30/69 (2025.01);
U.S. Cl.
CPC ...
G11C 11/2275 (2013.01); G11C 5/063 (2013.01); G11C 11/2273 (2013.01); H10B 51/20 (2023.02); H10D 30/0415 (2025.01); H10D 30/701 (2025.01);
Abstract

The integrated circuit structure includes a substrate and a memory cell over the substrate. The memory cell includes a channel layer, a first doped region, a second doped region, a first ferroelectric layer, and a first gate layer. The first doped region is at a first side of the channel layer and doped with a first dopant being of a first conductivity type. The second doped region is at a second side of the channel layer opposing the first side and doped with a second dopant being of a second conductivity type different from the first conductivity type. The ferroelectric layer is over the channel layer and between the first and second doped regions. The gate layer is over the ferroelectric layer.


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