The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2025

Filed:

Sep. 23, 2022
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Muir Kumph, Croton on Hudson, NY (US);

Oliver Dial, Yorktown Heights, NY (US);

John Michael Cotte, New Fairfield, CT (US);

David Abraham, Croton, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01P 5/02 (2006.01); G06N 10/40 (2022.01); H01P 11/00 (2006.01); H01R 12/72 (2011.01); H02J 50/05 (2016.01);
U.S. Cl.
CPC ...
H01P 5/028 (2013.01); G06N 10/40 (2022.01); H01P 5/02 (2013.01); H01P 11/003 (2013.01); H01R 12/721 (2013.01); H02J 50/05 (2016.02);
Abstract

A quantum computing chip device provides an edge based capacitive, intra-chip connection. A first chip includes a first signal line with a distal end positioned proximate to or on an edge of the first chip and a proximal end positioned away from the edge of the first chip. A second chip includes a second signal line with a distal end positioned proximate to or on an edge of the second chip and a proximal end positioned away from the edge of the second chip. The first signal line and the second signal line are configured to conduct a signal. The second signal line of the second chip is disposed in alignment for a capacitive bus connection to the first signal line of the first chip.


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