The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2025

Filed:

Apr. 26, 2022
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Julie Yang, Hsin-Chu, TW;

Chii Ming Wu, Taipei, TW;

Tzu-Chung Tsai, Hsinchu County, TW;

Yao-Wen Chang, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 23/00 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 24/05 (2013.01); H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 2224/02206 (2013.01); H01L 2224/02215 (2013.01); H01L 2224/03019 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05082 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/13026 (2013.01); H01L 2924/04941 (2013.01); H01L 2924/05432 (2013.01);
Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure disposed over a substrate. The interconnect structure includes a plurality of interconnect layers disposed within a dielectric structure. A bond pad structure is disposed over the interconnect structure. The bond pad structure includes a contact layer. A first masking layer including a metal-oxide is disposed over the bond pad structure. The first masking layer has interior sidewalls arranged directly over the bond pad structure to define an opening. A conductive bump is arranged within the opening and on the contact layer.


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