The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 11, 2025

Filed:

Aug. 19, 2021
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Purakh Raj Verma, Singapore, SG;

Kuo-Yuh Yang, Hsinchu County, TW;

Chia-Huei Lin, Hsinchu, TW;

Chu-Chun Chang, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01); H10B 61/00 (2023.01); H10B 63/10 (2023.01); H10N 50/80 (2023.01); H10N 70/00 (2023.01);
U.S. Cl.
CPC ...
H01L 23/10 (2013.01); H10B 61/00 (2023.02); H10N 50/80 (2023.02); H10N 70/801 (2023.02); H10B 63/10 (2023.02);
Abstract

An integrated circuit device includes a substrate; an integrated circuit area disposed on the substrate and comprising a dielectric stack; a seal ring disposed in the dielectric stack and around a periphery of the integrated circuit area; a cap layer on the dielectric stack; a trench around the seal ring and exposing a sidewall of the dielectric stack; a memory storage structure disposed on the cap layer; and a moisture blocking layer continuously covering the integrated circuit area and the memory storage structure. The moisture blocking layer extends to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.


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