The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Sep. 01, 2021
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Feng Yin, Hsinchu, TW;

Min-Kun Dai, Hsinchu, TW;

Chien-Hua Huang, Miaoli County, TW;

Chung-Te Lin, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10N 50/01 (2023.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01); H10N 50/85 (2023.01);
U.S. Cl.
CPC ...
H10N 50/01 (2023.02); H10B 61/22 (2023.02); H10N 50/80 (2023.02); H10N 50/85 (2023.02);
Abstract

Semiconductor structure and methods of forming the same are provided. An exemplary method includes providing a substrate having a first region and a second region, forming an array of memory cells over the first region of the substrate, and forming a memory-level dielectric layer around the array of memory cells. Each of the memory cells includes, from bottom to top, a bottom electrode, a memory material layer stack, and a top electrode. The exemplary method also includes forming a metal line directly interfacing a respective row of top electrodes of the array of memory cells. The metal line also directly interfaces a top surface of the memory-level dielectric layer.


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