The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 04, 2025

Filed:

Nov. 22, 2021
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Aniket Patil, San Diego, CA (US);

Durodami Lisk, San Diego, CA (US);

Hong Bok We, San Diego, CA (US);

Charles David Paynter, Encinitas, CA (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 24/16 (2013.01); H01L 25/50 (2013.01); H01L 2224/16227 (2013.01);
Abstract

A device comprising a first package and a second package coupled to the first package through a first plurality of solder interconnects. The first package includes a first substrate comprising at least one first dielectric layer and a first plurality of interconnects, and a first integrated device coupled to the first substrate. The second package includes a second substrate comprising at least one second dielectric layer and a second plurality of interconnects, a second integrated device coupled to a first surface of the second substrate, a third integrated device coupled to the first surface of the second substrate through a second plurality of solder interconnects and a first plurality of channel interconnects coupled to the first surface of the second substrate, wherein the first plurality of channel interconnects is located between solder interconnects from the second plurality of solder interconnects.


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